1. Field of the Invention
The present disclosure relates in general to timing circuits and, more particularly, to a clock-pulse generator.
2. Description of the Related Art
A clock-pulse generator frequently utilized in digital circuits is the oscillator shown in FIG. 1. It consists of an odd number of inverter elements connected to each other in the form of a ring and having a given input capacitance. A node H of the ring is connected to an output buffer, in this example another inverter, whose output OUT is the output of the generator. Given its input capacitance, each inverter constitutes a delay cell. With a view to permitting the activation and deactivation of the generator, the circuit is provided with an electronic switch M, in this example an N-channel MOS transistor, connected between the node H and ground and controlled by a signal RES that can assume either one or the other of two voltage values, typically those of the supply source of the circuit, corresponding to the logic states 0 and 1. When the switch is closed (RES=1), the generator is deactivated and the output OUT is in the logic state 0 (OUT=0). When the switch is open (RES=0), the oscillator can function and on the output (OUT) of the buffer there forms a train of pulses that, in the steady state, vary between 0 and 1 with a period 2n*dt, where n is the number of inverters in the ring and dt is the propagation delay of one cell. The duty cycle of the pulse train is typically 50% and is not easy to modify. This circuit has the drawback that, when the oscillator is started, its output, prior to attaining steady conditions, is subject to a transient during which both the amplitude and the frequency of the pulse train will vary. Consequently, whenever the output OUT has to be used for operations that call for the steady state oscillation frequency, one necessarily has to wait for the end of the transient.
FIG. 2 illustrates another known oscillator that comprises an odd number of inverting logic elements and a delay element connect in the form of a ring. The delay element is made in such a manner as to respond to a pulse at its input with a predetermined delay Δt with respect to the trailing edge of the input pulse and practically without delay with respect to the leading edge of this input pulse. A node H′ of the ring is connected to an output buffer, once again an inverter in this example, whose output is the output OUT of the generator. In order to permit activation and deactivation of the oscillator, the circuit is again provided with an electronic switch, an N-channel MOS transistor again indicated by M, connected between the node H′ and ground and controlled by a signal RES as in the circuit of FIG. 1. By this circuit, when a signal RES=0 causes transistor M to block, the oscillation begins practically without transients, so that the output OUT can be used immediately. As a general rule, however, the output signal has a very asymmetric duty cycle, because the time in which it is in the state 1 and the time in which it is in the state 0 are determined by delays that, in the greater part of practical applications, are very different from each other; in fact, we are here concerned with a relatively long delay due to the delay element and a relatively short delay deriving from the sum of the very brief switching delays of the inverters. The delay of the delay element can be easily modified, but that of the inverters is practically invariable, so that the duty cycle can be set to about 50% only for very high oscillation frequencies.